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august 2007 hys72d64301hbr?[5/6]?c hys72d128300hbr?[5/6]?c hys72d128321hbr?[5/6]?c hys72d256x20hbr?[5/6]?c 184-pin registered double-data-rate sdram module rdimm ddr sdram rohs compliant internet data sheet rev. 1.22
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 03292006-6n25-8r3i hys72d64301hbr?[5/6]?c, hys72d128300hbr?[5/6]?c, hys72d128321hbr?[5/6]?c, hys72d256x20hbr?[5/6]?c revision history: 2007-08, rev. 1.22 page subjects (major changes since last revision) all adapted internet edition all tables updated previous revision: 2006-03, rev. 1.21 all qimonda update previous revision: 2006-03, rev. 1.2 page subjects (major changes since last revision) 8 added product types to pc2700r previous revision: 2005-12, rev. 1.1
internet data sheet rev. 1.22, 2007-08 3 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 1overview 1.1 features ? 184-pin registered 8-byte dual-in-line ddr sdram module for pc, workstation and server main memory applications ? one rank 64m 72, 128m 72 organization , and two ranks 256m 72 organization ? standard double data rate synchronous drams (ddr sdram) with a single + 2.5 v ( 0.2 v) power supply and +2.6 ( 0.1 v) power supply for ddr400 ? built with ddr sdrams in fbga 60 package ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? ras-lockout supported t rap = t rcd ? all inputs and outputs sstl_2 compatible ? re-drive for all input signals us ing register and pll devices. ? serial presence detect with e 2 prom ? low profile modules form factor: 133.35 mm 28.58 mm (1.1?) 4.00 mm and 133.35 mm 30.48 mm (1.2?) ? standard reference card layout raw card a, b, c and f ? gold plated contacts ? rohs compliant product 1) table 1 performance 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. part number speed code ?5 ?6 unit speed grade component ddr400b ddr333b ? module pc3200?3033 pc2700?2533 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz
internet data sheet rev. 1.22, 2007-08 4 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 1.2 description the hys72d[64/128/256]xxxhbr ?[5/6]?c are low-profile versions of the standard regi stered dimm modules with 1.1- inch (28.58 mm) and 1.2-inch (30.40 mm) height for server applications. the low-profile dimm versions are available as 64m 72 (512mb), 128m 72 (1 gb), and 256m 72 (2 gb). the memory array is designed with double-data-rate synchronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 12 8 bytes contain factory programmed configuration dat a and the second 128 bytes are made available to the customer. table 2 ordering information table 3 address format product type 1) 1) all product types end with a place code designating the silicon-die revision. refe rence information available on request. exa mple: hys72d256320hbr?5?c, indicating rev.c die are used for sdram components. compliance code 2) 2) the compliance code is printed on the modul e labels and describes the speed sort (for example ?pc2700r?), the latencies (for example ?25331? means cas latency of 2.5 clocks, ro w-column-delay (rcd) latency of 3 clocks and row precharge latency of 3 clocks), spd code definition version 1, and the raw card used for this module. description sdram technology pc3200 (cl=3) hys72d64301hbr?5?c pc3200r?30331?a0 one rank 512 mbyte reg. ecc dimm 512 mbit ( 8) hys72d128300hbr?5?c pc3200r?30331?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321hbr?5?c pc3200r?30331?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256320hbr?5?c pc3200r?30331?f0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2700 (cl=2.5) hys72d64301hbr?6?c pc2700r?25331?a0 one rank 512 mbyte reg. ecc dimm 512 mbit ( 8) hys72d128300hbr?6?c pc2700r?25331?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128900hbr?6?c pc2700r?25331?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321hbr?6?c pc2700r?25331?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256320hbr?6?c pc2700r?25331?f0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d256920hbr?6?c pc2700r?25331?f0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) density organization memory ranks sdrams # of sdrams # of row/bank/ column bits refresh period interval 512 mb 64m 72 1 64m 8 9 13/2/11 8k 64 ms 7.8 ms 1 gb 128m 72 1 128m 4 18 13/2/12 8k 64 ms 7.8 ms 1 gb 128m 72 2 64m 8 18 13/2/11 8k 64 ms 7.8 ms 2 gb 256m 72 2 128m 4 36 13/2/12 8k 64 ms 7.8 ms
internet data sheet rev. 1.22, 2007-08 5 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 2 pin configuration the pin configuration of t he registered ddr sdram dimm is listed by function in table 4 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 5 and table 6 respectively. the pin numbering is depicted in chapter 1 . table 4 pin configuration of rdimm pin # name pin type buffer type function clock signals 137 ck0 i sstl clock signal 138 ck0 i sstl complement clock 21 cke0 i sstl clock enable rank 0 111 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc sstl note: 1-rank module control signals 157 s0 i sstl chip select of rank 0 158 s1 i sstl chip select of rank 1 note: 2-ranks module nc nc ? note: 1-rank module 154 ras i sstl row address strobe 65 cas i sstl column address strobe 63 we i sstl write enable 10 reset ilv- cmos register reset forces registered inputs low note: for detailed des- cription of the power up and power management see the application note at the end of data sheet address signals 59 ba0 i sstl bank address bus 1:0 52 ba1 i sstl 48 a0 i sstl address bus 11:0 43 a1 i sstl 41 a2 i sstl 130 a3 i sstl 37 a4 i sstl address bus 11:0 32 a5 i sstl 125 a6 i sstl 29 a7 i sstl 122 a8 i sstl 27 a9 i sstl 141 a10 i sstl ap i sstl 118 a11 i sstl 115 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 167 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 2 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 6 dq2 i/o sstl 8 dq3 i/o sstl 94 dq4 i/o sstl 95 dq5 i/o sstl 98 dq6 i/o sstl 99 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 19 dq10 i/o sstl 20 dq11 i/o sstl 105 dq12 i/o sstl pin # name pin type buffer type function
internet data sheet rev. 1.22, 2007-08 6 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 106 dq13 i/o sstl data bus 63:0 109 dq14 i/o sstl 110 dq15 i/o sstl 23 dq16 i/o sstl 24 dq17 i/o sstl 28 dq18 i/o sstl 31 dq19 i/o sstl 114 dq20 i/o sstl 117 dq21 i/o sstl 121 dq22 i/o sstl 123 dq23 i/o sstl 33 dq24 i/o sstl 35 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 126 dq28 i/o sstl 127 dq29 i/o sstl 131 dq30 i/o sstl 133 dq31 i/o sstl 53 dq32 i/o sstl 55 dq33 i/o sstl 57 dq34 i/o sstl 60 dq35 i/o sstl 146 dq36 i/o sstl 147 dq37 i/o sstl 150 dq38 i/o sstl 151 dq39 i/o sstl 61 dq40 i/o sstl 64 dq41 i/o sstl 68 dq42 i/o sstl 69 dq43 i/o sstl 153 dq44 i/o sstl 155 dq45 i/o sstl 161 dq46 i/o sstl 162 dq47 i/o sstl 72 dq48 i/o sstl 73 dq49 i/o sstl 79 dq50 i/o sstl 80 dq51 i/o sstl 165 dq52 i/o sstl pin # name pin type buffer type function 166 dq53 i/o sstl data bus 63:0 170 dq54 i/o sstl 171 dq55 i/o sstl 83 dq56 i/o sstl 84 dq57 i/o sstl 87 dq58 i/o sstl 88 dq59 i/o sstl 174 dq60 i/o sstl 175 dq61 i/o sstl 178 dq62 i/o sstl 179 dq63 i/o sstl 44 cb0 i/o sstl check bits 7:0 45 cb1 i/o sstl 49 cb2 i/o sstl 51 cb3 i/o sstl 134 cb4 i/o sstl 135 cb5 i/o sstl 142 cb6 i/o sstl 144 cb7 i/o sstl 5 dqs0 i/o sstl data strobes 8:0 note: see block diagram for corresponding dq signals 14 dqs1 i/o sstl 25 dqs2 i/o sstl 36 dqs3 i/o sstl 56 dqs4 i/o sstl 67 dqs5 i/o sstl 78 dqs6 i/o sstl 86 dqs7 i/o sstl 47 dqs8 i/o sstl 97 dm0 i sstl data mask 0 note: 8 based module dqs9 i/o sstl data strobe 9 note: 4 based module 107 dm1 i sstl data mask 1 note: 8 based module dqs10 i/o sstl data strobe 10 note: 4 based module 119 dm2 i sstl data mask 2 note: 8 based module dqs11 i/o sstl data strobe 11 note: 4 based module pin # name pin type buffer type function
internet data sheet rev. 1.22, 2007-08 7 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 129 dm3 i sstl data mask 3 note: 8 based module dqs12 i/o sstl data strobe 12 note: 4 based module 149 dm4 i sstl data mask 4 note: 8 based module dqs13 i/o sstl data strobe 13 note: 4 based module 159 dm5 i sstl data mask 5 note: 8 based module dqs14 i/o sstl data strobe 14 note: 4 based module 169 dm6 i sstl data mask 6 note: 8 based module dqs15 i/o sstl data strobe 15 note: 4 based module 177 dm7 i sstl data mask 7 note: 8 based module dqs16 i/o sstl data strobe 16 note: 4 based module 140 dm8 i sstl data mask 8 note: 8 based module dqs17 i/o sstl data strobe 17 note: 4 based module eeprom 92 scl i cmos serial bus clock 91 sda i/o od serial bus data 181 sa0 i cmos slave address select bus 2:0 182 sa1 i cmos 183 sa2 i cmos power supplies 1v ref ai ? i/o reference voltage 184 v ddspd pwr ? eeprom power supply pin # name pin type buffer type function 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq pwr ? i/o driver power supply 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd pwr ? power supply 3v ss gnd ? ground plane 11 18 26 34 42 50 58 66 74 81 89 93 100 pin # name pin type buffer type function
internet data sheet rev. 1.22, 2007-08 8 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 5 abbreviations for pin type table 6 abbreviations for buffer type 116 v ss gnd ? ground plane 124 132 139 145 152 160 176 other pins 82 v ddid ood v dd identification note: pin in tristate, indicating v dd and v ddq nets connected on pcb 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173 nc nc ? not connected pins not connected on qimonda rdimm?s pin # name pin type buffer type function abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable (jedec standard) nc not connected (jedec standard) abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or.
internet data sheet rev. 1.22, 2007-08 9 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module figure 1 pin configuration 184 pins, registered mppd0020 pin 001 pin 003 pin 005 pin 007 pin 009 pin 011 pin 013 pin 015 pin 017 pin 019 pin 021 pin 023 pin 025 pin 027 pin 029 pin 031 pin 033 pin 035 pin 037 pin 039 pin 041 pin 043 pin 045 pin 047 pin 049 pin 051 - - - - - - - - - - pin 002 pin 004 pin 006 pin 008 pin 010 pin 012 pin 014 pin 016 pin 018 pin 020 pin 022 pin 024 pin 026 pin 028 pin 030 pin 032 pin 034 pin 036 pin 038 pin 040 pin 042 pin 044 pin 046 pin 048 pin 050 pin 052 - - - - - - - - - - v ref dqs0 nc dq09 nc dq10 dq00 dq01 dq02 dq03 reset dq08 dqs1 nc dq11 pin 054 pin 056 pin 058 pin 060 pin 062 pin 064 pin 066 pin 068 pin 070 pin 072 pin 074 pin 076 pin 078 pin 080 pin 082 pin 084 pin 086 pin 088 pin 090 pin 092 dq17 dq18 a5 dqs3 dq27 cb00 a0 ba1 - - - - - - - - - - - - - - - - pin 053 pin 055 pin 057 pin 059 pin 061 pin 063 pin 065 pin 067 pin 069 pin 071 pin 073 pin 075 pin 077 pin 079 pin 081 pin 083 pin 085 pin 087 pin 089 pin 091 cke0 dq16 dqs2 a9 a7 dq19 dq24 dq25 a4 dq26 a2 a1 cb01 dqs8 cb02 cb03 - - - - - - - - - - - - - - - - v ss v ss v dd v ss v ddq v ddq v ss v ss v dd v ddq v ss v ddq v ss v dd v ss v dd v ss v ddq v ss v ddq v ss v dd v ss v ddid dq32 dq33 dq34 ba0 dq40 we cas dqs5 dq43 nc dq49 nc dq50 dq56 dq58 sda - - - - - - - - - - - - - - - - - - - - dqs4 dq35 dq41 dq42 dq48 nc dqs6 dq51 dq57 dqs7 dq59 nc scl - - - - - - - - - - - - - - - - - - - - pin 093 pin 095 pin 097 pin 099 pin 101 pin 103 pin 105 pin 107 pin 109 pin 111 - - - - - - - - - - pin 094 pin 096 pin 098 pin 100 pin 102 pin 104 pin 106 pin 108 pin 110 pin 112 - - - - - - - - - - dq05 dq00/dqs9 dq07 nc nc dq15 dm1/dqs10 dq14 cke1/nc nc a12/nc dq21 dm2/dqs11 dq22 dq23 a6 dq29 dm3/dqs12 dq30 dq31 cb5 ck0 a10/ap dq04 dq06 nc dq13 dq15 pin 114 pin 116 pin 118 pin 120 pin 122 pin 124 pin 126 pin 128 pin 130 pin 132 pin 134 pin 136 pin 138 pin 140 pin 142 pin 144 dq20 a11 a8 dq28 a3 dq04 ck0 dm8/dqs17 cb06 cb07 - - - - - - - - - - - - - - - - pin 113 pin 115 pin 117 pin 119 pin 121 pin 123 pin 125 pin 127 pin 129 pin 131 pin 133 pin 135 pin 137 pin 139 pin 141 pin 143 dq37 dm4/dqs13 dq39 dq44 dq45 s0 dm5/dqs14 dq46 nc dq52 a13/nc dm6/dqs15 dq55 nc dq61 dm7/dqs16 dq63 sa0 sa2 - - - - - - - - - - - - - - - - v ddq v ddq v ddq v dd v dd v ss v ss v ss v ss v ddq v ss v ss v ddq v ddq v dd v ddq v ss v ddq v ddq v ss v ddq v ss v dd v ss pin 146 pin 148 pin 150 pin 152 pin 154 pin 156 pin 158 pin 160 pin 162 pin 164 pin 166 pin 168 pin 170 pin 172 pin 174 pin 176 pin 178 pin 180 pin 182 pin 184 dq36 dq38 ras s1/nc dq47 dq53 dq54 dq60 dq62 sa1 v ddspd - - - - - - - - - - - - - - - - - - - - pin 145 pin 147 pin 149 pin 151 pin 153 pin 155 pin 157 pin 159 pin 161 pin 163 pin 165 pin 167 pin 169 pin 171 pin 173 pin 175 pin 177 pin 179 pin 181 pin 183 - - - - - - - - - - - - - - - - - - - -
internet data sheet rev. 1.22, 2007-08 10 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 3 electrical characteristics 3.1 operating conditions table 7 absolute maximum ratings attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be rest ricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause ir reversible damage to the integrated circuit. parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) pd ? 1 ? w ? short circuit output current i out ?50? ma?
internet data sheet rev. 1.22, 2007-08 11 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 8 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck > 166 mhz 2) 2) ddr400 conditions apply for all clock frequencies above 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) 3) under all conditions, v ddq must be less than or equal to v dd . output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) 4) peak to peak ac noise on v ref may not exceed 2% v ref.dc . v ref is also expected to tr ack noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 6) 6) inputs are not recognized as valid until v ref stabilizes. input low (logic0) voltage v il(dc) ? 0.3 v ref ? 0.15 v 6) input voltage level, ck and ck inputs v in(dc) ? 0.3 v ddq + 0.3 v 6) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 6)7) 7) v id is the magnitude of the difference between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current v i ratio 0.71 1.4 ? 8) 8) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test = 0 v 9) 9) values are shown per pin. output leakage current i oz ?5 5 a dqs are disabled; 0 v v out v ddq 9) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v
internet data sheet rev. 1.22, 2007-08 12 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 9 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dq s inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see co mponent data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changi ng twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2 ; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changin g on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2 ; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changin g on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
internet data sheet rev. 1.22, 2007-08 13 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 10 i dd specification for hys72d[64/128/256]xxxhbr?5?c product type hys72d64301hbr?5?c hys72d128300hbr?5?c hys72d128321hbr?5?c hys72d256320hbr?5?c unit note 1)2) 1) module i dd is calculated on the basis of component i dd and includes register and pll currents 2) test condition for maximum values: v dd =2.7v, t a =10c organization 512 mb 1 gb 1 gb 2 gb 72 72 72 72 1rank 1rank 2ranks 2ranks ?5 ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. typ. max. i dd0 1050 1240 1890 2210 1660 1910 3120 3570 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 1270 1470 2200 2530 1880 2140 3430 3890 ma 3)4) 4) dq i/o (i ddq ) currents are not included into calculations: module i dd values will be measured diffe rently depending on load conditions i dd2p 360 440 670 780 670 780 1290 1460 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 830 940 1360 1510 1360 1510 2410 2650 ma 5) i dd2q 510 600 960 1120 960 1120 1870 2140 ma 5) i dd3p 460 530 860 970 870 970 1670 1850 ma 5) i dd3n 920 1050 1540 1730 1540 1730 2770 3090 ma 5) i dd4r 1360 1510 2380 2620 1970 2190 3610 3980 ma 3)4) i dd4w 1400 1560 2470 2710 2020 2240 3700 4070 ma 3) i dd5 1670 2120 3280 4130 2290 2800 4510 5490 ma 3) i dd6 330 390 640 740 640 740 1270 1430 ma 5) i dd7 2390 2770 4450 5140 3010 3450 5680 6500 ma 3)4)
internet data sheet rev. 1.22, 2007-08 14 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 11 i dd specification for hys72d[64/128/256]xxxhbr?6?c product type hys72d64301hbr?6?c hys72d128300hbr?6?c hys72d128900hbr?6?c hys72d128321hbr?6?c hys72d256320hbr?6?c hys72d256920hbr?6?c unit note 1)2) 1) module i dd is calculated on the basis of component i dd and includes register and pll currents 2) test condition for maximum values: v dd =2.7v, t a =10c organization 512 mb 1 gb 1 gb 2 gb 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks ?6 ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. typ. max. i dd0 1000 1140 1790 2020 1530 1720 2860 3180 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 1160 1360 2000 2330 1700 1940 3060 3490 ma 3)4) 4) dq i/o (i ddq ) currents are not included into calculations: module i dd values will be measured diffe rently depending on load conditions i dd2p 340 410 600 700 600 700 1120 1280 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 740 840 1180 1310 1180 1310 2060 2260 ma 5) i dd2q 470 560 860 1000 860 1000 1630 1890 ma 5) i dd3p 430 500 770 880 770 880 1460 1640 ma 5) i dd3n 830 940 1370 1520 1370 1520 2440 2690 ma 5) i dd4r 1210 1410 2090 2420 1740 1990 3150 3580 ma 3)4) i dd4w 1250 1450 2180 2510 1790 2030 3240 3670 ma 3) i dd5 1510 1950 2930 3780 2040 2530 4000 4940 ma 3) i dd6 320 390 580 680 580 680 1110 1270 ma 5) i dd7 2150 2490 3980 4580 2690 3070 5040 5750 ma 3)4)
internet data sheet rev. 1.22, 2007-08 15 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 3.2 a.c. timing parameters table 12 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck )t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. (t cl , t ch ) ? min. (t cl , t ch )? ns 2)3)4)5) dq & dqs high-impedance time from ck/ck t hz ?+0.7?+0.7ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9)
internet data sheet rev. 1.22, 2007-08 16 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) dq & dqs low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2?t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ?t qhs ?t hp ?t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ?t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)10) auto-refresh to active/auto- refresh command period t rfc 65 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)11) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)12) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1?t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); ddq = 2.6 v 0.1 v, dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing re ference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
internet data sheet rev. 1.22, 2007-08 17 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 7) t hz and t lz transitions occur in the same access ti me windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) a maximun of eight autorefresh commands can be posted to any gi ven ddr sdram device 11) the specific requirement is that dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specificationsof the device. w hen no writes were previously in progress on the bus, dqs will be transitioni ng from hi-z to logic low. if a previous write wa s in progress, dqs could be high, low at this time , depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
internet data sheet rev. 1.22, 2007-08 18 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 4 spd codes table 13 spd codes for hys72d[64/1 28/256]3[00/01/20/21]hbr?5?c product type hys72d64301hbr?5?c hys72d128321hbr?5?c hys72d128300hbr?5?c hys72d256320hbr?5?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc3200r? 30331 pc3200r?30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0c 0c 5 number of dimm ranks 01 02 01 02 6 data width (lsb) 48 48 48 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 11 error correction support 02 02 02 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 04 04 14 error checking sdram width 08 08 04 04 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04
internet data sheet rev. 1.22, 2007-08 19 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 18 cas latency 1c 1c 1c 1c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 26 26 26 26 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 70 70 70 70 27 t rpmin [ns] 3c 3c 3c 3c 28 t rrdmin [ns] 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 31 module density per rank 80 80 01 01 32 t as, t cs [ns] 60 60 60 60 33 t ah, t ch [ns] 60 60 60 60 34 t ds [ns] 40 40 40 40 35 t dh [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 43 t ckmax [ns] 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 dimm pcb height 01 01 01 01 product type hys72d64301hbr?5?c hys72d128321hbr?5?c hys72d128300hbr?5?c hys72d256320hbr?5?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc3200r? 30331 pc3200r?30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.22, 2007-08 20 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 48 - 61 not used 00 00 00 00 62 spd revision 10 10 10 10 63 checksum of byte 0-62 c7 c8 41 42 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 37 37 37 37 74 part number, char 2 32 32 32 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 31 31 32 77 part number, char 5 34 32 32 35 78 part number, char 6 33 38 38 36 79 part number, char 7 30 33 33 33 80 part number, char 8 31 32 30 32 81 part number, char 9 48 31 30 30 82 part number, char 10 42 48 48 48 83 part number, char 11 52 42 42 42 84 part number, char 12 35 52 52 52 85 part number, char 13 43 35 35 35 86 part number, char 14 20 43 43 43 product type hys72d64301hbr?5?c hys72d128321hbr?5?c hys72d128300hbr?5?c hys72d256320hbr?5?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc3200r? 30331 pc3200r?30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.22, 2007-08 21 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 1x 1x 1x 1x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 product type hys72d64301hbr?5?c hys72d128321hbr?5?c hys72d128300hbr?5?c hys72d256320hbr?5?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc3200r? 30331 pc3200r?30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.22, 2007-08 22 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 14 spd codes for hys72d[64/1 28/256]3[00/01/20/21]hbr?6?c product type hys72d64301hbr?6?c hys72d128321hbr?6?c hys72d128300hbr?6?c hys72d256320hbr?6?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0c 0c 5 number of dimm ranks 01 02 01 02 6 data width (lsb) 48 48 48 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 11 error correction support 02 02 02 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 04 04 14 error checking sdram width 08 08 04 04 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 0c 0c 0c 0c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 26 26 26 26 22 component attributes c1 c1 c1 c1
internet data sheet rev. 1.22, 2007-08 23 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 27 t rpmin [ns] 48 48 48 48 28 t rrdmin [ns] 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 31 module density per rank 80 80 01 01 32 t as, t cs [ns] 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 34 t ds [ns] 45 45 45 45 35 t dh [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 43 t ckmax [ns] 30 30 30 30 44 t dqsqmax [ns] 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 dimm pcb height 01 01 01 01 48 - 61 not used 00 00 00 00 62 spd revision 10 10 10 10 63 checksum of byte 0-62 61 62 db dc 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f product type hys72d64301hbr?6?c hys72d128321hbr?6?c hys72d128300hbr?6?c hys72d256320hbr?6?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.22, 2007-08 24 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 37 37 37 37 74 part number, char 2 32 32 32 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 31 31 32 77 part number, char 5 34 32 32 35 78 part number, char 6 33 38 38 36 79 part number, char 7 30 33 33 33 80 part number, char 8 31 32 30 32 81 part number, char 9 48 31 30 30 82 part number, char 10 42 48 48 48 83 part number, char 11 52 42 42 42 84 part number, char 12 36 52 52 52 85 part number, char 13 43 36 36 36 86 part number, char 14 20 43 43 43 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 1x 1x 1x 1x product type hys72d64301hbr?6?c hys72d128321hbr?6?c hys72d128300hbr?6?c hys72d256320hbr?6?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.22, 2007-08 25 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 product type hys72d64301hbr?6?c hys72d128321hbr?6?c hys72d128300hbr?6?c hys72d256320hbr?6?c organization 512 mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 4) 2 ranks ( 4) label code pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 pc2700r? 25331 jedec spd revision rev 1. 0 rev 1.0 rev 1.0 rev 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.22, 2007-08 26 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module table 15 spd codes for hys72d[128/256]90x0hbr?6?c product type hys72d128900hbr?6?c hys72d256920hbr?6?c organization 1 gbyte 2 gbyte 72 72 1 rank ( 4) 2 ranks ( 4) label code pc2700r?25331 pc2700r?25331 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex 0 programmed spd bytes in e2prom 80 80 1 total number of bytes in e2prom 08 08 2 memory type (ddr = 07h) 07 07 3 number of row addresses 0d 0d 4 number of column addresses 0c 0c 5 number of dimm ranks 01 02 6 data width (lsb) 48 48 7 data width (msb) 00 00 8 interface voltage levels 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 11 error correction support 02 02 12 refresh rate 82 82 13 primary sdram width 04 04 14 error checking sdram width 04 04 15 t ccd [cycles] 01 01 16 burst length supported 0e 0e 17 number of banks on sdram device 04 04 18 cas latency 0c 0c 19 cs latency 01 01 20 write latency 02 02 21 dimm attributes 26 26 22 component attributes c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75
internet data sheet rev. 1.22, 2007-08 27 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 24 t ac sdram @ cl max -0.5 [ns] 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 27 t rpmin [ns] 48 48 28 t rrdmin [ns] 30 30 29 t rcdmin [ns] 48 48 30 t rasmin [ns] 2a 2a 31 module density per rank 01 01 32 t as, t cs [ns] 75 75 33 t ah, t ch [ns] 75 75 34 t ds [ns] 45 45 35 t dh [ns] 45 45 36 - 40 not used 00 00 41 t rcmin [ns] 3c 3c 42 t rfcmin [ns] 48 48 43 t ckmax [ns] 30 30 44 t dqsqmax [ns] 28 28 45 t qhsmax [ns] 50 50 46 not used 00 00 47 dimm pcb height 01 01 48 - 61 not used 00 00 62 spd revision 10 10 63 checksum of byte 0-62 db dc 64 manufacturer?s jedec id code (1) 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f product type hys72d128900hbr?6?c hys72d256920hbr?6?c organization 1 gbyte 2 gbyte 72 72 1 rank ( 4) 2 ranks ( 4) label code pc2700r?25331 pc2700r?25331 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex
internet data sheet rev. 1.22, 2007-08 28 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 67 manufacturer?s jedec id code (4) 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 69 manufacturer?s jedec id code (6) 51 51 70 manufacturer?s jedec id code (7) 00 00 71 manufacturer?s jedec id code (8) 00 00 72 module manufacturer location xx xx 73 part number, char 1 37 37 74 part number, char 2 32 32 75 part number, char 3 44 44 76 part number, char 4 31 32 77 part number, char 5 32 35 78 part number, char 6 38 36 79 part number, char 7 39 39 80 part number, char 8 30 32 81 part number, char 9 30 30 82 part number, char 10 48 48 83 part number, char 11 42 42 84 part number, char 12 52 52 85 part number, char 13 36 36 86 part number, char 14 43 43 87 part number, char 15 20 20 88 part number, char 16 20 20 89 part number, char 17 20 20 90 part number, char 18 20 20 91 module revision code 1x 1x 92 test program revision code xx xx product type hys72d128900hbr?6?c hys72d256920hbr?6?c organization 1 gbyte 2 gbyte 72 72 1 rank ( 4) 2 ranks ( 4) label code pc2700r?25331 pc2700r?25331 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex
internet data sheet rev. 1.22, 2007-08 29 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number (1 - 4) xx xx 99 - 127 not used 00 00 product type hys72d128900hbr?6?c hys72d256920hbr?6?c organization 1 gbyte 2 gbyte 72 72 1 rank ( 4) 2 ranks ( 4) label code pc2700r?25331 pc2700r?25331 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex
internet data sheet rev. 1.22, 2007-08 30 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 5 package outlines figure 2 package outline raw card a - l-dim-184-21 notes 1. general tolerances +/- 0.15 2. drawing according to iso 8015 ? ? ? ! "# x ! # ! " " ? " ! # - ! 8 # ? ? $ e t a i l o f c o n t a c t s ? ? ! # " " u r r m a x a l l o w e d - ) . ? " ! #
internet data sheet rev. 1.22, 2007-08 31 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module figure 3 package outline raw card c - l-dim-184-22 notes 1. general tolerances +/- 0.15 2. drawing according to iso 8015 ? ? ! "# ? ! x ! # " " ? " ! # ? ? !" # $ e t a i l o f c o n t a c t s ? ? # !" # ? - ! 8 " u r r m a x a l l o w e d - ) .
internet data sheet rev. 1.22, 2007-08 32 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module figure 4 package outline raw card b - l-dim-184-23 notes 1. general tolerances +/- 0.15 2. drawing according to iso 8015 - ! 8 # ? ? ? ? x # !" ! " # ! # !" ? " " ! # # " ! $ e t a i l o f c o n t a c t s ? ? ? ? - ) . " u r r m a x a l l o w e d
internet data sheet rev. 1.22, 2007-08 33 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module figure 5 package outline raw card f ? l-dim-184-25 notes 1. general tolerances +/- 0.15 2. drawing according to iso 8015 ! "# ! ! ? ? # !" ? " ? " ! # - ! 8 # ? ? " ! # ? - ) . " u r r m a x a l l o w e d $ e t a i l o f c o n t a c t s ? !" # ? , $ ) -
internet data sheet rev. 1.22, 2007-08 34 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 6 application note power up and power management on ddr registered dimms (according to jedec ballot jc-42.5 item 1173) 184-pin double data rate (ddr) registered dimms include two ne w features to facilitate cont rolled power-up and to minimize power consumption during low power mode. one feature is externally controlle d via a system-generated reset signal; the second is based on module detection of the input clocks. th ese enhancements permit the modules to power up with sdram outputs in a high-z state (eliminating risk of high current dissipati ons and/or dotted i/os), and result in the powering-down o f module support devices (registers and phase-locked loop) when the memory is in self-refresh mode. the new reset pin controls power dissipation on the module?s registers and ensures that cke and other sdram inputs are maintained at a valid ?low? level during power-up and self refresh. when reset is at a low level, all the register outputs are forced to a low level, and all differential register input rece ivers are powered down, resulting in very low register power consumption. the reset pin, located on dimm tab #10, is driven from the system as an asynchronous signal according to the attached details. using this function also permits the system and di mm clocks to be stopped durin g memory self refresh operation, while ensuring that the sdrams stay in self refresh mode. table 16 function for reset as described in the table above, a low on the reset input ensures that the clock enable (cke) signal(s) are maintained low at the sdram pins (cke being one of the 'q' signals at t he register output). holding cke low maintains a high impedance state on the sdram dq, dqs and dm outputs ? where they will remain until activated by a valid ?read? cycle. cke low also maintains sdrams in self refresh mode when applicable. the ddr pll devices automatically detect clock activity above 20mhz. when an input clock frequency of 20mhz or greater is detected, the pll begins o peration and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95mhz). if the clock input fr equency drops below 20mhz (actual detect frequency will vary by vendor), the pll vco (voltage controlled oscillator) is sto pped, outputs are made high-z, an d the differential inputs are powered down ? resulting in a total pll current consumption of less than 1ma. use of this low power pll function makes the use of the pll reset (or g pin) unnecessary, and it is tied inactive on the dimm. this application note describes the required and optional system sequences associated with the ddr registered dimm 'reset ' function. it is important to note that all references to cke refer to both cke0 and cke1 for a 2-bank dimm. because reset applies to all dimm register devices, it is therefore not possible to uniquely control cke to one physical dimm bank through the use of the reset pin. register inputs register outputs 1) 1) x : don?t care, hi-z : high impedance, qo: data latc hed at the previous of ck risning and ck falling reset ck ck data in (d) data out (q) h rising falling h h h rising falling l l h l or h l or h x qo h high z high z x illegal input conditions l x or hi-z x or hi-z x or hi-z l
internet data sheet rev. 1.22, 2007-08 35 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module power-up sequence wi th reset ? required 1. the system sets reset at a valid low level. this is the preferred default state during power-up. this input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that cke is at a stable low-level at the ddr sdrams. 2. the power supplies should be initialized according to th e jedec-approved initialization sequence for ddr sdrams. 3. stabilization of clocks to the sdram the system must drive clocks to the applic ation frequency (pll operation is not assured until the input clock r eaches 20mhz). stability of cl ocks at the sdrams will be affe cted by all applicable system clock devices, and time must be allotted to permit all clock devic es to settle. once a stable clock is received at the dimm pll, the required pll stabilizat ion time (assuming power to the dimm is stab le) is 100 microseconds. when a stable clock is present at the sdram input (driven from the pll), the ddr sdram requires 200 sec prior to sdram operation. 4. the system applies valid logic levels to the data inputs of the register (address and contro ls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system de signer. one option is to apply an sdram ?nop? command (wit h cke low), as this is the first command defined by the jedec initialization sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs to be consistent with the st ate of the register outputs. 5. the system switches reset to a logic ?high? level. the sdram is no w functional and prepared to receive commands. since the reset signal is asynchro nous, setting the reset timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. the system must maintain stable register inputs until normal re gister operation is at tained. the registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. during this time the syst em must maintain the valid logi c levels described in step 5. it is also a func tional requireme nt that the registers maintain a low stat e at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time (t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 7. the system can begin the jedec-defined ddr sdra m power-up sequence (according to the jedec-pproved initialization sequence). self refresh entry (reset low, clocks powered off) ? optional self refresh can be used to retain data in ddr sdram dimms even if the rest of the system is powered down and the clocks are off. this mode allows the ddr sdrams on the dimm to reta in data without external clo cking. self refresh mode is an ideal time to utilize the reset pin, as this can reduce re gister power consumption (reset low deactivates register ck and ck, data input receivers, and data output drivers). ? the system applies self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: the commands reach the ddr sdram one clock later due to the additional register pi pelining on a registered dimm. after this command is issued to the sdram, all of the ad dress and control and clock input conditions to the sdram are don?t cares? with the exception of cke. ? the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensure s that cke, and all other control and address signals, are a stable low-level at the ddr sdrams. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required. ? the system turns off clock inputs to the di mm. (optional) a. in order to reduce di mm pll current, the clock inputs to the dimm are turned off, resulting in high-z clock inputs to both the sdrams and the registers. this must be done after the reset deactivate time of the regist er (t (inact) ). the deactiva te time defines the time in which the clocks and the control and address signals must maintain valid levels after reset low has been applied and is spec ified in the regi ster and dimm documentation. b. the system ma y release dimm address and control inputs to high-z. this can be done after the reset deactivate time of the register. the deac tivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during this operation.
internet data sheet rev. 1.22, 2007-08 36 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module ? the dimm is in lowest power self refresh mode. self refresh exit (reset low, clocks powered off) ? optional 1. stabilization of clocks to the sdram. the system must drive clocks to the app lication frequency (pll operation is not assured until the input clock reaches ~20mhz). stability of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devic es to settle. once a stable clock is received at the dimm pll, the required pll stabilization time (assuming po wer to the dimm is stable) is 100 microseconds. 2. the system applies valid logic levels to the data inputs of the register (address and contro ls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system de signer. one option is to apply an sdram ?nop? command (wit h cke low), as this is the first command defined by the jedec self refr esh exit sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs , to be consistent with the state of the register outputs. 3. the system switches reset to a logic ?high? level. the sdram is no w functional and prepared to receive commands. since the reset signal is asynchronous, reset timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. the system must maintain stable register inputs until normal re gister operation is at tained. the registers have an activation time that allows the clock receivers, input receivers, and out put drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 2. it is al so a functional requirement that the registers maintain a low state at the cke outputs to guar antee that the ddr sdrams continue to receive a low level on cke. register activation time (t (act ) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 5. system can begin the jedec-defined ddr sdram self refresh exit procedure. self refresh entry (reset low, clocks running) ? optional although keeping the clocks running increases power consumpti on from the on-dimm pll during self refresh, this is an alternate operating mode for these dimms. 1. system enters self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: the commands reach the ddr sdram one clock later due to the additional register pi pelining on a registered dimm. after this command is issued to the sdram, all of the ad dress and control and clock input conditions to the sdram are don?t cares ? with the exception of cke. ? the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ens ures that cke is a stable low-level at the ddr sdrams. ? the system may release dimm address and control inpu ts to high-z. this can be done after the reset deactivate time of the register (t (inact) ). the deactivate time describes the ti me in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during the operation. ? the dimm is in a low power, self refresh mode. self refresh exit (reset low, clocks running) ? optional 1. the system applies valid logic levels to the data inputs of the register (address and contro ls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system de signer. one option is to apply an sdram ?nop? command (wit h cke low), as this is the first command defined by the self refresh exit sequence (ideally this would be a ?nop desele ct? command). a second option is to apply low levels on all of the register inputs to be consistent with the st ate of the register outputs.
internet data sheet rev. 1.22, 2007-08 37 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 2. the system switches reset to a logic 'high' level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. the system must maintain stable register inputs until normal re gister operation is at tained. the registers have an activation time that allows the clock receivers, input receivers, and out put drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 1. it is al so a functional requirement that the registers maintain a low state at the cke outputs in or der to guarantee that the ddr sdrams continue to receive a low level on cke. this activation time , from asynchronous switching of reset from low to high, until the registers are stable and ready to accept an input signal, is t (act ) as specified in the register and dimm documentation. 4. the system can begin jedec defined d dr sdram self refresh exit procedure. self refresh entry/exit (reset high, clocks running) ? optional as this sequence does not involve the use of the reset function, the jedec standard sdram specification explains in detail the method for entering and exiting self refresh for this case. self refresh entry (reset high, clocks powered off) ? not permissible in order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on cke, or the cl ocks are powered off and reset is asserted low according to the sequence defined in this application note. in the case where reset remains high and the clocks are powered off, the pll dr ives a high-z clock input into the register clock input. without the low level on reset an unknown dimm state will result.
internet data sheet rev. 1.22, 2007-08 38 03292006-6n25-8r3i hys72d[64/128/256]xxxhbr?[5/6]?c registered double-data-rate sdram module 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 a.c. timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table of contents
edition 2007-08 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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